1. Technical Field
The present disclosure relates to a circuit for generating a voltage on a plate of a capacitor coupled to an SRAM memory cell.
2. Description of the Related Art
Static Random Access Memory (SRAM) is used in many applications. SRAM typically consumes little power and has fast read/write times.
FIG. 1 shows a common SRAM cell 20. The SRAM cell 20 comprises a first inverter 26 and a second inverter 28 in a cross-coupled configuration. A bit is stored at the bit storage node 22. The bit storage node 22 is coupled to the input of the first inverter 26 and to the output of the second inverter. A complementary bit node 24 is coupled to the output of the first inverter 26 and the input of the second inverter 28. The complementary bit node 24 carries the opposite value from the bit storage node 22. Each of the inverters is powered by a high supply voltage and a low supply voltage, usually ground. When the bit storage node 22 receives a high voltage, the first inverter 26 outputs a voltage equal to the low supply voltage to the input of second inverter 28. When the input of the first inverter 26 receives a low voltage, the first inverter 26 outputs a voltage equal to the high supply voltage VDD to the input of the second inverter 28. The cross-coupled configuration of the two inverters 26, 28 reinforces the values at the bit storage node 22 and the complementary bit node 24. The reinforcing configuration of the first and second inverters helps ensure the stability of the SRAM cell 20. Access transistors 30 and 32 permit reading from and writing to the memory cell 20.
SRAM can be particularly advantageous compared to other types of random access memory (RAM). Both read and write operations on an SRAM cell are particularly fast compared to read and write operations in other types of memories such as a dynamic random access memory (DRAM) or EEPROM. SRAM cells also do not need to be continuously refreshed. This means that an idle SRAM uses very little power.
Because SRAM is fast for both reading and writing and consumes relatively little power, SRAM is used in a very large variety of systems. Almost all portable electronic devices have one or more SRAM arrays. Most personal computers have one or more SRAM arrays. Modems, calculators, electronic toys, etc. . . . all use SRAM arrays.
In particular, SRAM arrays are finding use in internal medical devices. Internal medical devices such as pacemakers and internal defibrillators employ SRAMs because of the low power consumption and high reliability. The battery in an internal medical device is preferred to be able to last a very long time. Thus a memory array in the internal medical device should consume very little power.
Over the years SRAM cells have been made smaller and smaller. As individual SRAM cells have shrunk, they have become more susceptible to soft errors. One example of a soft error is a memory cell 20 being rewritten when no write process has been called for. Various forms of radiation may by chance encounter the SRAM array and cause a soft error. One common form of radiation that may cause soft errors is an alpha particle. An alpha particle is helium nucleus consisting of two positively charged protons and two neutrons. Thus the alpha particle has a net positive charge. An alpha particle that travels through an SRAM array will cause a multitude of electrons to follow in its wake. If these electrons encounter an input or an output of a memory cell 20 carrying a positive charge, the state of the cell 20 may erroneously be rewritten.
Soft errors can be particularly problematic for internal medical devices carrying SRAM arrays. A person travelling on airplanes, passing through security detectors, X-ray machines or other equipment may be more susceptible to alpha particles or other types of radiation that may destroy the stored data. Improper function of a memory array of an internal defibrillator or pacemaker can be very dangerous to the health of the person in whom the defibrillator or pacemaker is installed.
FIG. 2 illustrates a prior art SRAM cell 34 designed to be more resistant to soft errors. The structure of the SRAM cell 34 in FIG. 2 is similar to that of FIG. 1. But the SRAM cell 34 of FIG. 2 additionally comprises two capacitors 36, 38 coupled in series between the bit storage node 22 and the complementary bit node 24. A common node 44 has a voltage regulator VPLG coupled to it. The function of the two capacitors 36, 38 and the voltage regulator is to further reinforce the value stored at the bit storage node 22. When the bit storage node 22 is high, the first plate 40 of the first capacitor 36 charges to the high value. Stray electrons dragged to the bit storage node 22 by an alpha particle will not be enough to bring the bit storage node 22 low and rewrite the value stored in the cell 34. The excess positive charge stored on the first plate 40 of the first capacitor 36 ensures that bit will not be rewritten. If the bit storage node 22 is low, then the complementary bit node 24 is high and the first plate 42 of the second capacitor 38 is charged to the high value while the first plate 40 of the first capacitor 36 is brought low.
As can be seen in FIG. 2, the second plates 46, 48 of the first and second capacitors 36, 38 are both coupled to the common node 44. The second plates 46, 48 receive a capacitor supply voltage VPLG from a voltage regulator, not shown in this figure. The capacitor supply voltage VPLG is approximately midway between the high supply voltage VDD and the low supply voltage GND. Thus the second plates 46, 48 of the capacitors 36, 38 are continuously driven by a voltage regulator with feedback and bias currents to be held at a voltage midway between VDD and GND. This configuration further reinforces the value stored at the bit storage node 22.
Generating and supplying the capacitor supply voltage VPLG in the prior art has been very power intensive. A full regulated power supply with various feedback paths is used. Such a power supply has bias currents, various current mirrors, feedback paths and other circuits that are assured of maintaining the voltage, but at significant power cost. The power supply for VPLG thus consumes a large amount of power even through its sole use is to hold data in the SRAM cell. An SRAM that consumes more power may be unsuitable for use in internal medical devices.